`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/05/07 21:47:32
// Design Name: 
// Module Name: axi_master_w
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module axi_master_w(
input logic ACLK,
input logic ARESETn,
//AW
output logic AWVALID,
output logic [31:0] AWADDR,
output logic [7:0] AWLEN,
output logic [2:0] AWSIZE,
output logic [1:0] AWBURST,
input logic AWREADY,
//W
output logic WVALID,
output logic [31:0] WDATA,
output logic WLAST,
output logic [3:0] WSTRB,
input logic WREADY,
//B
input logic BVALID,
input logic [1:0] BRESP,
output logic BREADY
    );
//发出一次写请求
task write_req;
   input [31:0] wr_addr;
   input [31:0] wr_len;
   //
   AWVALID=0;
   AWADDR=wr_addr;
   AWLEN=wr_len;
   @(posedge ACLK);
   AWVALID=1;
   wait(AWREADY==1'b1);
   $display("write request:wr_addr=%d,wr_len=%d",wr_addr,wr_len+1);
   @(posedge ACLK);
   AWVALID=0;
endtask   
//写数据
task write_data;
    input [31:0] wr_len;
    input [31:0] start_num;
	//
	$display("write data:wr_len=%d,start_num=%d",wr_len,start_num);
	WVALID=0;
	WDATA=0;
	@(posedge ACLK);
	for(int i=0;i<wr_len;i=i+1)
	begin
	    if(i==wr_len-1)
		    WLAST=1;
		else
		    WLAST=0;
	    WDATA=start_num+i;
		WVALID=1;
		wait(WREADY==1'b1);                    //完成一次握手
		@(posedge ACLK);
	end
	WLAST=0;
	WVALID=0;
endtask
//
initial
begin
    AWBURST=2'b00;
	AWSIZE=3'd2;
	WSTRB=4'b1111;
end
//write request
initial
begin
    AWVALID=0;
    #107
	write_req(0,7);
	write_req(16,7);
	write_req(32,7);
	write_req(48,7);
	write_req(96,15);
	write_req(64,15);
end
//write data
initial
begin
    WVALID=0;
    #107
	write_data(8,1);
	write_data(8,17);
	write_data(8,33);
	write_data(8,49);
	write_data(16,97);
	write_data(16,65);
end
//BREADY
always_ff@(posedge ACLK,negedge ARESETn)
if(~ARESETn)
    BREADY<=0;
else if(BVALID&&~BREADY)
    BREADY<=1;
else if(BVALID&&BREADY)
    BREADY<=0;
//inst slave
//axi_slave U(.*);
/*.ACLK,
.ARESETn,
//AR
input logic ARVALID,
input logic [31:0] ARADDR,
input logic [7:0] ARLEN,
output logic ARREADY,
//R
output logic [31:0] RDATA,
output logic RVALID,
output logic RLAST,
output logic [1:0] RRESP,
input logic RREADY,
//AW
input logic AWVALID,
input logic [31:0] AWADDR,
input logic AWLEN,
input logic [2:0] AWSIZE,
input logic [1:0] AWBURST,
output logic AWREADY,
//W
input logic [31:0] WDATA,
input logic WVALID,
input logic WLAST,
input logic [3:0] WSTRB,
output logic WREADY,
//B
output logic BVALID,
output logic [1:0] BRESP,
input logic BREADY*/
//    );
endmodule
